It has been a common practice for companies involved in the development of computer systems and software also to provide a separate utility system having the ability to monitor internal computer operations. Typically, such utility systems are used by programmers to "snap" internal computer and memory states at selected points of program operation. These points may be identified, for example, by the execution of program instructions or read/write operations at particular computer memory addresses or blocks of addresses. For example, one typical utility circuit is a block address matcher used to detect transactions at computer memory addresses within a range, or block, defined by specified upper and lower boundary addresses. The circuitry required to implement these utility systems has been traditionally large because of the technology involved. This was not a significant problem in the past, however, because the utility systems were generally used by system designers for noncommercial laboratory use only.
With the advent of modern large-scale integrated circuits resulting in smaller and smaller computer systems and the recognition that the software of complex computing systems is never completely debugged, it is becoming desirable to include utility debugging packages as integral system parts for field debugging. Since utility packages have no role in the normal functional operation of computing systems, it is essential that the physical space occupied by such a package be as small as possible. Even with the use of large-scale integrated circuits in the utility packages, the circuit space required using conventional techniques may be objectionable in comparison to the space occupied by a computer. For example, one conventional technique of implementing computer memory block address matchers in a utility package is to wire in cascade a sufficient number of magnitude comparators to account for each address bit of a computer memory addressing structure. For a 24-bit address bus, for example, a block address matcher using this conventional technique would require six 8-bit buffers for storing an upper and a lower block address for the memory block to be monitored; six 4-bit comparators for each of the upper and lower block addresses, plus some incidental output logic. This amounts to about 18 or 19 integrated circuit chips requiring housing space on the order of perhaps three circuit packs. It would be highly desirable to reduce this space requirement to no more than one circuit pack, especially if the circuitry is to be an integral part of a computer. Related goals would be to accomplish this with circuitry that is less expensive and more conservative of power than conventional techniques.